Design Of SRAM And Compiler Technology

With the rapid progress of microelectronics technology, it is undoubtedly that 21st century will be the century of information. Moreover, semiconductor memories have been the cornerstone of whole information age. In the large family of semiconductor memories, Static random access memories (SRAMs) are an indispensable part because of their broad applications. Considerable attention has been paid to the design of low-power, hign-performance SRAMs since they are a critical component in both hand-held devices and high-performance processors. A key in improventing the performance of the system is to use an optimum sized SRAM.In this thesis, after a brief account of the classification, application and development of semiconductor at home and abroad, the structure and work pricinple of SRAM are dicussed. Then, memory cell array and some parts of peripheral circuits used in SRAM, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. Furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi-stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128Kbit and IMbit SRAM. What's more, we have studied compiler technology applied in the designing course of a IMbit full CMOS SRAM from the pointview of methology. Finally, we present the corresponding algorithm. The compiled SRAMs realize highspeed data-read and consume low power with the density ranging from 128Kbit to IMbit. This thesis deserves further study when one wants to design other kinds of memory compiler.