VLSI Implementation Of EBCOT Decoder In JPEG2000 System

JPEG2000 is the next generation digital still image compression standard introduced by ISO/ITU-T (International Standard Organization/International Telecommunication Union). Being Different from JPEG, JPEG2000 is based on DWT (Discrete Wavelet Transform) and EBCOT (Embedded Block Coding with Optimized Truncation) algorithm. The codestream produced by JPEG2000 can be truncated and optimized, and so it can used in many applications. JPEG2000 also have better compression performance than JPEG.EBCOT is the core algorithm of JPEG2000 standard. Data compression and rate control are both realized through EBCOT. It has the feature of complex computing, bit-level operation and time consuming. So it is hard to accelerate and optimize using general processor or DSP. It is necessary for us to design a specific architecture for EBCOT.In this thesis, I will first introduce the JPEG2000 standard and its main modules: Discrete Wavelet Transform, Quantization, Compress Coding and Codestream Organization. Secondly I will analyze the EBCOT algorithm in detail. In hardware design, I will first study and compare several optimization method. Then based on the compare results, I will propose a VLSI architecture of EBCOT decoder with attention to both speed and hardware consume. This architecture is based on skipping method in BPC (Bit-plane coding) module and has three stage of pipeline at BAC (Binary Arithmetic Coding), it can perform well in the JPEG2000 decode system. In addition, an EBCOT decoder architecture based on pass-parallel method is also proposed in this thesis.