Study On Still Image Coding And VLSI Architecture Based On JPEG2000

This thesis firstly researches the algorithms in the still image compression field during the past years. It concentrates on several efficient wavelet-based approaches Then , a new algorithm called "Adaptive Subband Decomposition And Context-Modeling Based Image Coding" is proposed in this thesis. It has the better compression performance than the SPHIT and simultaneously preserved the property of embedded zerotree coding. Then, this thesis focuses on the analysis and hardware implementation of the newest still image compression standard ?JPEG2000. Several efficient architectures about the core processing units in JPEG2000 are proposed. They can be used to the JPEG2000-based image compression system and other wavelet-based or bit-plane-coding-based multimedia system. The main contribution and creative work are listed in this thesis:I Research about the still image compression:a)After a careful and in-depth study on the wavelet-based still image compression an new modified zero-tree-based algorithm is proposed to improve the compression efficiency thanks to two new techniques ?"Adaptive Subbands Decomposition and Context-Modeling Based Arithmetic Coding".b)Analyze the newest still image compression standard ?JPEG2000. Researches devote to the first part of standard. Then, a behavioral module using C language is developed, which has been verified by the standard software system.II.Research about the VLSI architecture of JPEG2000 standard:An optimized flow has been introduced by the analysis of JPEG2000. This flow is better suitable for the hardware implementation than the software-based flow recommended in JPEG2000. According to the optimized flow, several efficient architectures about the core procession units of JPEG2000 have been proposedincluding the Discrete Wavelet Transformation (DWT) unit, Bit Plane Coding (BPC) unit and Arithmetic Coding (MQ) unit. Many techniques such as, the embedded extension algorithm, the reducing scaling coefficients multiplication algorithm, the pipelined data-path, the multi-coding-pass parallelism and scan-window-based technique, and memory reuse technique etc. have been using in our proposed architectures. Compared with others architectures, the performance in power, speed and area etc. has been improved.III The verification of JPEG2000 processing systemAccording to the characters of JPEG2000, a software and hardware cooperating system has been proposed. In this system, the core algorithms are implemented in hardware to accelerate the processing. The pre- and post- processing parts of JPEG2000 are implemented using the software in the computer. The UART port is used to transfer the processing data. Finally, the system is implemented in the Xilinx's Virtex II FPGA - based development system.In the finial, the conclusion about the thesis and the future work are given.