| With the advance of network and multimedia technology, information technology has great development. People look forward to high quality image information. But the transmission of information is limited by the bandwidth. And the storage of information is limited by the capacity of memory. JPEG standard is not able to afford the requirement of still image compression any more.JPEG2000 is a new image compression standard, developed under the auspices of IOS/IEC JTCI/SC29/WG1 in January,2001.Compared with JPEG standard, the JPEG2000 standard not only has better compression performance, but also has many excellent features.JPEG2000 provides quality scalability, resolution scalability, region– of– interest (ROI) coding, and supports both lossy and lossless coding in the same framework.The bottleneck of the JPEG2000 system results from the high computation complexity of EBCOT, which is comprised of fractional Bit-plane coder and the MQ arithmetic coder. In design of this paper, the architecture of EBCOT coder and the software flow of Bit-plane coding algorithm in JPEG2000 standard are analyzed. On the basis of predecessor's research, a parallel VLSI architecture of Bit-plane coder is proposed. The architecture is based on bit-plane parallel and the column-based processing method. In the architecture, a most significant bit-plane detection circuit detects the most significant bit-plane. A bit-plane control module scans the code block data and transforms the Sign-Magnitude data. Bit planes are coded by context format (CF) modules in parallel. In context format module, three pass modules code one by one at three times of code block scanning. Four identical coding elements implement 4 samples coding at one time in pass modules. Buffers receive bit stream which comes from context format modules and send out bit stream in turn.The design of system of RTL Level is described by verilog HDL in the top-down way. After simulating in Modelsim, we synthesize the design in Xilinx ISE. |
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