Research On The On-Chip Bus And Testing Technology In The SoC Platform

The Intellectual Properties (IP) reuse based System on Chip (SoC) design technology has been widely used in the Integrated Circuit (IC) industry. It can not only significantly reduce the Time to Market (TTM) and the system cost, but also allow to integrate more functions and to improve the IC design productivity. It has become one of the mainstream technology in the industry now days.SoC interconnection architecture and SoC testing are two of the most important technologies. As to the former, the bus based communication architecture has been popularly used in SoC design. In the context of SoC testing, with the chips becoming more and more complex, it becomes more and more important to design SoC testing in the early stage of the design process. The studies on the boundary scan based SoC testing technology turn out to be relatively mature.In this thesis, we study these two technologies in an 8-bit SoC platform, where the MCU soft core IP called HGD08R01 was designed by the VLSI institute of Hefei University of Technology. We first designed a bus protocol based HGD08R01, and then designed various peripheral IP to establish this SoC platform. The JTAG module was one of such IPs. The main contribution of the study is summarized as follows.1. Designing the on chip bus architecture and protocols in the 8-bit SoC platform;2. Designing the JTAG IP module for the platform, including the JTAG top-level architecture design, sub-module design and functional verification of JTAG.