Research Of Design For Digital System Testability Based On Boundary-Scan

With the development of technology, PCB components of new electronic product install closely and pins are dense which make measuring points lack, so traditional test equipment such as neilsbed and probe has difficult in solving these. Considering the fact that nowadays most CPLD, FPGA, MCU, DSP and other important components which are widely used in digital circuits have supported the function of boundary-scan, as well as the trend of digitalization of power electronic equipment, this paper brings forward and realizes a kind of boundary-scan test system based on virtual instrument after analyzing the new features of digital testing, hoping to provide a general and effective tool for the testing of digital system.This boundary-scan test system is composed of a PC host and a JTAG controller. On the basis of analyzing boundary-scan test theory and IEEE Std 1149.1, this paper discusses to complete generating and loading of testing vector, saving and analyzing of testing response using PC host, in order to implement the whole testing process of integrity, interconnection, function and cluster. A graphic user interface is developed to help users finish the whole process. The development of controller is completed with simulating software and parallel port configured download cable for understanding details of data transmission and TAP state, which is different from using traditional TSET BUS CONTROLLER.This paper chooses USB logic analyzer as a typical tested object, and carries through a second develop to design it supporting IEEE 1149.1 boundary-scan function for testability. The application example of testing logic analyzer illuminates the boundary-scan test system's using method and testing process, also shows the demonstration flow of digital system's full boundary-scan test process.