Testability Realization Based On FPGA Digital Integrated Circuit

Nowadays, the integrated circuit industry is developing rapidly. With increasingly rich powerful, high speed, low power consumption, encapsulation of miniaturization of IC products, some questions followed. First, IC functions increase, a single chip tends to integrate millions of components, pin number increase, integration becomes higher. Secondly, encapsulation technology’s complication and miniaturization, which causes more narrow of connections between each unit, more densely between each pin. These above absolutely reduce the chip physical access and increase the time, power consumption and the difficulty of IC test. Traditional testing technology based on physical contact pace cannot keep up with the development of the IC, IC test encountered bottleneck problem. In that context, the design for test methods(DFT) was put forward, the characteristics of automation and simplicity efficiently overcome the above problems, which were applied to various fields quickly.The main work of the paper use the standard of IEEE1149.1 to complete the design of BST structure. Using the boundary scan controller which has a 16 bit FSM, control the TAP and each register to actualize download, shift, update, capture the test vector or the test response. Finally, the control circuit, the circuit-under-test and the analysis of circuit is downloaded to the development board, which to achieve the digital circuit fault diagnosis and the purpose of self-testing. In this paper, using LFSR provides some binary pseudo random number as the test vector generation, which to extract the effective vectors. The design in the QuartusII software environment, using Verilog HDL prepared to achieve the function of each part of the boundary scan test circuit, the final realization of the overall design by FPGA.