The Design Of HDLC Controller Based On FPGA

HDLC is used broadly as a protocol of Data Link Layer. The subset of HDLC is adopted by X.25, ISDN and Frame-Relay. But most of the present HDLC products are from abroad. The ASICs of HDLC include Motorola's MC92460, ST's MK5025, Zarlink's MT8952B and so on. Many companies, such as Innocor, Xilinx, have delivered the IP Core which implements HDLC protocol, but these cores can only be used after paying for license. Furthermore, the purchased ASIC and IP Core are restricted practically. So it is significant to design HDLC products of which we own the property.CRC checking is the critical element of HDLC protocol, by which both sides of communication can detect whether burst errors have happened. Although all CRC technique work on the same principle, the implementations of CRC can be different and up to now there are still new algorithm appearing continually. The implementations of CRC have three kinds of methods:1) software methods, 2) serial methods implemented by hardware, 3) parallel methods implemented by hardware. The serial methods can handle only one bit once, while the parallel methods which perform much faster can compute multiple bits once .The Work of this dissertation includes two aspects.Firstly, based on the symbol polynomial, the parallel CRC algorithm of arbitrarily multiple bits is proposed and proved theoretically. Furthermore, the method of computation of CRC through this algorithm is illustrated with the computation of a byte and the related VHDL module is given. After contrast and analysis, it is indicated that both CPD and Area of the proposed parallel CRC algorithm are optimized.Secondly, based on the Top-Down design method, the design of the HDLC protocol controller is described behaviorally. The design is implemented onXilinx's FPGA product.