Design And Verification Of 8051IP Core Based On FPGA

As a very important branch of computer, single-chip microcomputer(SCM) has received significant attention since it was invented in 1976. Particularly the MCS-51 series SCM which was produced by the USA Intel company, has been widely used in varies industries in our country for its high integration, robustness, flexibility, low cost, and so on. This thesis implements the IP core of 8051 MCU using VHDL, and the FPGA is selected as the simulation platform.This paper firstly introduces the related basic knowledge of FPGA and the development tools of EDA, the principle analysis of 8051SCM and the function of each module. By using top-down design method for 8051 CPU conducted IP core module partition, using VHDL language to program of each module, and designing the corresponding test data. In the modelsim simulation platform, the timing and function verification of each module were completed. The accomplished instruction set is fully compatible with the 8051 single-chip Microsoft instruction, so this design is achieved the desired result. Finally, this paper conducted a comprehensive simulation to the whole 80C51IP core in Altera company EP1K100FC484 chip, and built a simple application circuit to complete the IP core validation.The realization of 8051IP core can accelerate the development of education informatization in some respect, and further expand the programmable logic devices scope of application, complex proprietary chip to high-end and complicated application, making the concept of IP resources to be more reuse common application, the application of the embedded system based on FPGA design provides a broad avenue of research.