Research And Development Of Reusable Verification Platform Of SoC

With the increasing size and design complexity of SoC, verification becomes more and more difficult. It will cost a half or more than 70% efforts on the development cycle of SoC, and the ability of verification is far more behind than the capacity of design and production. Currently, the verification has become the main bottleneck in the design of SoC and constrained its application. The application of verification methodology has been an international hotspot and the key technology. The purpose of new rising OVM verification methodology (Open Verification Methodology) is to provide a highly efficient verification method and to become a standard for unifying the verification platform. So it is considered to be the most promising developing methodology to break the bottleneck.For today's verification challenges, first this paper makes a deep study of the basic principles, the frameworks and the implements of OVM in the analysis of advantages and disadvantages of the traditional verification environment. Particularly, it proposes an efficient and complete test plan to achieve the reusability and extendibility of functional tests with the demand of SoC verification. Secondly, the verification platform (prototype) of a design project is developed by the SystemVerilog language based on OVM with the technology of transaction-level modeling (TLM) and object-oriented programming to achieve the hierarchy and modularity. During the simulation of RTL, each module is running and collecting the error reports in real-time. It makes the platform (prototype) modular, reusable and efficient. Finally, this gives some suggestions on how to optimize the SoC verification platform and how to improve its reusability and efficiency.