MP3 Decoder IP Design And Reusability Research

Currently, most MP3 decoders were implemented in software based on DSP or RISC processor,resulting in higher power consumption and cost. Meantime, it is not easy to use them as IP cores in SoC applications. In this research work, the design, verification and reusability of a hard-wired MP3 decoder IP are discussed. Power is optimized from architecture, implementation and algorithm levels synthetically. The result is a complete synthesizable Verilog code IP, reusable in SoC applications.This paper detailedly analyzes the MP3 decoding algorithms and data dependency of decoding steps, puts forward a new"parallel and pipelining"architecture, the decoding clock frequency can be reduced to under 10MHz. Aiming at hard-wired implementation, some optimization methods are put forward: (1) After Huffman decoding, there is a continuous zero district in high frequency portion of frequency lines. Utilizing this characteristic, the amount of computations for requantilizing, stereo processing, alias reconstruction and IMDCT can be reduced. Also the memory access times can be reduced, resulting in lower power consumption. (2) By modifing the address generation logic, the"reorder"step can be bypassed, thus the memory access power is reduced. (3) Huffman decoding, requantilizing and stereo processing pipelining executing,the memory access times can be reduced, resulting in lower power consumption. In algorithm level, utilizing the symmetry of trigonometric functions, a new method is implemented to reduce the complexity of IMDCT and subband synthesis, meeting the requirements of pipelining execution.The requirements and their solutions for IP reusability are discussed from various aspects including RTL coding, design data management, design for test, function verification and interface design. The interface design and verification methods of the VTD010 MP3 decoder IP are described specifically. As a case study, the IP's reusability in mobile phone application is discussed.Experimental results indicate that the MP3 decoder IP developed meets ISO/IEC 11172-4 compatible test and is superior in low power consumption as compared with other known implementations.