Design And Development Of FPGA Based High-speed Bus For Control System

Control system internal bus is the channel for high-speed information exchange between I/O cards, communication cards and controllers, also is the hub of the whole system for real-time and management data transmission. With hot-swappable, redundant, high transmission speed, short communication distance features, control system internal bus must have high reliability, high fault tolerance, high real-time properties. Foreign major manufacturers of control system often take security measures for system bus research results. Combined with a new type of hybrid control system research, the design and development of high-speed bus located in the control device unit layer were completed, focusing on solving real-time, reliability and scalability of the design requirements.The high speed bus architecture and design specifications were proposed based on the research of the characteristics of the typical control system internal bus at home and abroad. The high-speed bus physical layer protocol was designed, which was based on multipoint-low-voltage differential signaling (M-LVDS) standard and soft clock data recover (SCDR.) to achieve 256 Mbps serial communication and to ensure that the cycles of bus scheduling was less than lms for 32 nodes. The DC balance and data transmission reliability were achieved by 8b/10b encoding and cyclic redundancy code. And topology, communication distance, redundancy and bus expansion were detailed defined.Multi-path optimization selection network redundancy through real-time link state maintenance was used in data link layer to ensure reliable communications while maximizing bandwidth utilization, and to provide multiple path selection strategies for the application layer and user layer. Data link layer protocol defined the bus device type, protocol data unit format, data transmission, etc., to achieve the link scheduling, clock synchronization, broadcast multicast, and other functions.The design was implemented on Xilinx XC3S400A FPGA and the prototype development was completed. Detailed tests of the whole system in real time, efficiency and redundancy performance were done. Results showed that communication speed and real-time performance were improved significantly compared with the current mainstream bus of control system, and the needs of upper applications were met to the greatest degree.