Design Of Low Voltage Differential Signaling Receivers

With the development of information technology, the social demand of data transmission grows increasingly. So, we need a new interface technique to realize more fast data transmission, with low noise and low power dissipation meanwhile. LVDS (Low Voltage Differential Signaling) is an international general interface standard, applied for high-speed signal transmission, which uses low voltage swing high-speed differential signal to transmit data. LVDS has many advantages such as high-speed, low power dissipation, low noise and low cost. At present, Technology of Low Voltage Differential Signaling receivers have become a research focus in high-speed interface chip field.Based on the research of high-speed signal transmitting theoryand equalizer technology, this paper make a deep analysis of LVDS receiving circuit, and make a design using the SMIC standard 0.18μm CMOS technology. The LVDS receiving circuit is composed by pre-amplifier, adaptive equalizer , voltage comparator and fail-safe circuit. Pre-amplifier used the structure of folded cascade op amplifier, it can restrain input common modemode range effective; the adaptive equalizer is the research emphasis of this paper. Based on the deep research of equalizer technology, this paper presents a design of an adaptive equalizer applied for receiving circuit, which provides a high frequency adcance controlled port to equalizer using the feedback signal out of a adaptive loop, to compensate for the distortion of high frequency component during signal transmission and achieve low bit error rate; The compensated differential sinal input to the voltage comparator, and the input differential signal was transferred into CMOS logic signal.Simulation analysis of whole LVDS circuit was made in this paper, the result shows that our design can meet the requirement of system design. In the end, layout design of the whole LVDS receiving circuit was presented.