Research On Image Capture And Preprocessing System Based On CycloneII Series FPGA

Image capture and preprocessing system is to obtain the images and features of the objective world. It can complete image signal capture, storage and processing. Nowadays image capture and preprocessing system is widely used in industry, medical, military and many other fields. Image capture and preprocessing system based on FPGA (Field Programmable Gate Array) is now emphasized and widely researched. FPGA is a kind of programmable logic device which is widely used. It can be dynamically configured with flexibility, and also it can realize pipeline and parallel technology in design. It has high-speed processing ability and universal transplantation, which is very suitable for image real-time processing.Domestic research of image processing system based on FPGA is developing in succession. But compared with foreign research, there occurs a big gap in hardware platform design, system software establishment, input and output resources configurations, optimization of processing algorithm etc. Under this background, a system is established in this paper with high-performance CycloneII series FPGA EP2C35F672C6 of Altera as key processor, MT9M011 digital CMOS image sensor of MICRON as image capture device and SDRAM storage chip A2V64S40CTP-G7 of PSC as memory device. On the basis of general design, by researching system interface logic control, resources configuration, algorithm processing module and establishing image capture and processing system based on FPGA, the function of image real-time capture, storage, preprocessing and display is achieved in this design.The basic principles of each function modules, the characteristics and design demands of data communication are all analyzed in this paper. On this situation, with FPGA parallel technology and pipeline program concept, image capture module, color reversion module, SDRAM controller module and VGA display controller module are designed and achieved by using Verilog hardware description language on QuartusII8.0 platform. The design results of every modules and the whole system are observed and verified by embedded logic analyser SignalTapII in QuartusII8.0 and oscilloscope. And the ultimate results satisfy the system design demands.Considering image preprocessing algorithm, the basic principles and characteristics of using median filter to reduce noise are mainly analyzed, and combined with real-time processing and system logic resources demands, an improved median filtering algorithm is implemented on FPGA platform using Verilog hardware description language. Then the designed median filtering module is simulated and tested,and a verification scheme is also formulated. Lastly in this paper, by using the power consumption analysis tool:Power play early estimation in QuartusII, power consumption of the whole system is given. And some methods to reduce power consumption are presented. Finally, the general logic resources consumption is analyzed, and the results show that the whole system consumes small amount of FPGA hardware resources, that provides abundant resources for subsequent processing.