The Design Of 10bits 10MSPS Pipelined A/D Convertor And The Algorithm Modification

This paper adopted the technology of pipelined architecture A/D conversion and designed a A/D convertor of 10 bits resolution factor,10 MSPS sampling speed with nine-stage pipelined architecture of 1.5 bit per stage,it can achieve the negative redundancy error correction between -1/4Vref ~ +1/4Vref. Through researching the algorithm of the pipelined architecture and analyzing its principle of quantization and encoding ,got the ability of negative redundancy technology in the different parts of the error correction areas,and found that the traditional pipelined architecture actually achieved the end-off method,which can bring more quantization error. So a modified algorithm based on the traditional architecture is presented.The algorithm achieved a pipelined architecture of rounding method by adjusting the quantization level per stage,can reduced the quantization error. Used the software of MATLAB to simulate the whole conversion process of pipelined architecture A/D convertor to prove the correctness of the algorithm.According to the step-by-step convertsion flow , following the sequence of ADSC,DASC,subtraction,magnify and output the data to the next stage, through verified pipelined architecture A/D convertors with various precisions,proved this algorithm can achieve the rounding method structure well.In addition,this paper presented the circuit structures of the major modules.Finally,used the Hspice to simulate each module,making the simulating result meet the design requirements . Modified the decoding circuit,the decoding process can be achieved only by two addtion stages by using equivalence different with several addition stages before,also can adopt the mature adder circuit to speed the decoding circuit,this has been proved the feasibility by compiling verilog codes.