Design And Optimization Of Video Encoder Chip

Compared with the previous video compression standards, although the newest international standard H.264/AVC and the national standard AVS which we have our own intellectual property provide much higher compression efficiency, they have much more hardware complexity for the design of video codec. So the video encoder chip needs optimization. This paper focuses on design and optimization of video encoder.The optimization of video encoder chip includes system level one and circuit level one in this paper. Under the needs of requirement, system level optimization design presents a system architecture which makes hardware implementation easier, which includes arithmetic level optimization, the arrangement of pipeline and so on. Circuit level optimization includes chip-area optimization by resource sharing base on reusable teclinology's methodology and speed optimization of the critical path.System level optimization in the design of intra prediction module adopts a new optimization method, which is much more suitable for hardware design than traditional optimization method. After using this method, speed of the system improves considerablely at the price of increace of bit rate by 3-4 percent. For the design of deblocking filter module, we propose an architecture which has a higher speed by rearranging the deblocking order which also decreases the operating frequency of RAM.Circuit level optimization in the design adopts reuse methodology and increase parallel methodology. Reuse methodology, which based on the prediction similarity of different intra prediction modes, adopts reconfigurable intra predictor. For the adaptivity of deblocking filter brings judge branches which increases the circuit delay, Increase parallel methodology is used in the design in order to decrease the critical path delay.