Design And Implementation Of Intra Prediction And Deblock Filter In AVS Based On FPGA

The application of multimedia video compression technique grows very rapidly with the development of information technology and digital signal processing transmission. Image compression technology is got more and more attention. AVS standard is a source coding standard of China with independent intellectual properties, whose applications are mainly SDTV and HDTV.Compared with H.264/AVC, It has many advantages such as intellectual property rights clear, high technical performance. AVS standard adopts amounts of new technologies, such as including of intra prediction, adaptive block size motion compensation, integer cosine transformation, quarter-pixel interpolation and context-based adaptive binary arithmetic coding. Because the AVS standard has a complete standard system of system, video, audio and copyright management for media, the AVS could provide comprehensive solution for audio/video coding/decoding.Design and Implementation of Intra-prediction and Loop-filter module of AVS based on FPGA are discussed in this paper. The XC5VFX100T FPGA of Virtex-5 series FPGA produced by Xilinx was designed as the hardware platform of this design. At first, Basic knowledge of AVS and FPGA is introduced briefly in the paper. Then the architectures of two important modules in AVS coder, which is Intra-prediction and Loop-filter, are studied and discussed. At the same time, in order to insure the correctness of the design, it is simulated all the time.According to AVS standard, we improve the arithmetic of intra prediction mode selection. An easy and effective fast mode selection for intra prediction is proposed in this paper. In this way, we can decrease the time of encoding and the complication of intra-prediction.Then we propose a rational hardware design of intra-prediction module, introduce the function and structure of all the module, and set up an efficient storage mechanism. According to the simulation, the module occupys about 10% resource of XC5VFX100T FPGA. This design can satisfy the request of real-time.On the base of analysis the loop-filter algorithm, this paper proposed an efficient architecture to implement the loop-filter for AVS. It employed a new filter processing in turns of vertical boundaries inserted with horizontal boundaries and uses register array to transpose and store intermediate date. In the unite of filter, ping-pang store technique and pipeling technique is introduced.In this way, the time of filter is decreased largely. As a result, it greatly decreased the accessing bandwidth and memory resource on chip and speeded up the processing speed of the filter, so it can satisfy the requirement of real-time encoder of high definition video.