Hardware Design Of Intra Prediction And Deblocking Filter In H.264/AVC Video Decoder

H.264/AVC as a new generation of multimedia video standards, compared to previous video standards such as MPEG series H.26X series, H.264can substantially improve the compression ratio at the same image quality, so it has a very broad application prospects. However, the advantages of the H.264are at the price of increase calculation complexity in encoder and decoder, therefore efficient hardware architecture is need to meet the requirements of real-time video decoding.This paper analyzes the H.264Standard, especially intra-prediction and deblocking filter. According to the requirements of the design, this paper proposes the hardware architecture of intra prediction and deblocking filter. In intra prediction module, in order to speed up, adjust the decoding order of the4x4block prediction model. Design a general processing element, this processing element improves the reusability of hardware resources to save hardware resources. In order to improve the system performance, four parallel processing elements, plane mode precomputation and mode predictor are adopted. In deblocking filter module, according to analysis critical path of the filtering process, five-stage pipeline architecture is adopted to improve system performance. Improve the boundary filter order to reduce memory access. Clock gating is used to reduce system power consumption. And a reusable computing unit is design in order to increase the reuse of hardware resources. Transpose cache is aimed to speed up read pixels. In order to reduce the memory bandwidth, different pixels have difference storage mechanisms.The intra prediction and deblocking filter modeling complete use VerilogHDL, this paper also write C reference model according to JM9.4. Use different methods to obtain the test stimuli, function simulation have been completed on each module by using digital circuit simulation tool VCS. The experiment results show that the two modules are both correct. Two modules are synthesized by using (TSMC)0.131μm technology library. The frequency of the two modules can both work in50M. Synthesis and verification results show that two modules design are meet the require goals of this project.The verification and synthesis results indicate that the design of Intra-prediction and Deblocking-filter have achieved requirement.