Research Of The Test Generation Algorithm For The Combinational Circuit

Integrated circuit is a modular circuit that assembles multiple electronic components on the silicon board to fulfill some specific fuction. IC is the most important part in the electronic devices, and it undertakes the functions of operating and storing. IC can be applied to almost all the electronic devices for civil use and military project. IC can be called the absolute"heart"for the computery, the digital domestic electricity, the communication and so on.With the development of the microelectronic technique, the scale of the integrated circuits become more and more large, the structure become more and more complex, and the test generation for the integrated circuits is becoming increasingly difficult and time consuming. The traditional test generation algorithms are extremely inefficient for the large-scale circuits. Consequently, new and cost-effective algorithms are imperative research subjects today.The single stuck-at fault model is an earliest fault model researched in the world for combinational circuit, and it is also the one used mostly. Practice shows that the test set for single stuck-at fault can test other kind fault, e.g. multi-fault and bridging fault, if only fault coverage for single stuck-at fault attains above 90%. Because the probability of happening multi-fault for system is big during debug phase and the possibility of happening single fault is bigger during usage phase, the test generation problem for single stuck-at fault is the hot spot of research in the world. On paper, it has been solved earlier than 60 times. But theoretical analyze proofs that time complexity for automatic test generation is an NP-completeness problem. As the augment of circuit scale, test generation becomes more and more difficult. Therefore, accelerating test generation and improving its efficiency are noticed all along.This paper uses the single stuck-at fault model and selectes the combinational circuits as research targets. It mainly aims to improve the fault coverage and reduce the test generation time. The main contents are as following:...