Debug System Of RAM Chip And Its ASIC Design

A new debug system is developed in our project for the analysis performance of RAM chips, and a key ASIC chip is designed for the new system. We can use the new system to automatically debug the external RAMs of electronic systems. In the new debug system, test data can be reconfigured and different testing routes can be set according to the specific debug requirements, it is of high efficiency, high coverage and configurability. In order to present the development process and principle of the ASIC chip, this thesis firstly is to outline the general methods of IC chip debug, and then detail on the circuit principle, fault types and debug methods of RAM chip. Considering the specifics of external RAM chip's faults, we have modified the direct access debugging method, and implemented it in our ASIC chip.The thesis work conducts the design of our ASIC chip in a typical top-down way. At first, we illustrate the general design of the debug system, define the major modules, including CPU interface module, debug module and RAM interface module. After that, we detail on design of every module, included the design of detailed functional diagrams, state machine and associate interface timing. Where, we used Verilog HDL to design the functions of our ASIC chip at RTL level, and implemented it with FPGAs. The innovations of our work are that: A debug module based on transaction-oriented verification methods offers high debugging speed, and the modified method of direct access debug not only can detect faults of RAM cells and surrounding circuits, but also effectively avoid misjudgment due to wire fault.