The Design Of A Subharmonic Sampling Phase-Locked Oscillator

In this paper, a research of a Ku-band subharmonic sampling phase-locked (PLL) oscillator is presented. There are three parts in this paper. The First part is analysis and design of the subharmonic sampling phase-locked loop. The theory of subharmonic sampling PLL is elaborately analyzed and loop parameter calculation formulae are introduced, and then the design rule is obtained in order to reach the best noise performance. A high performance integrated circuit is used as sampling phase detector and two-order active filter is used as loop filter. Circuit to extend capture range is designed to increase the stability of PLL. Secondly, a Ku-band Vt-DRO is designed . Oscillator and its phase noise performance are elaborately analyzed by ADS software, which is also used to optimize DRO circuit. The main experimental data are shown as following, phase noise:-95dbc/Hz@10KHz,-112dbc/Hz@100KHz, output power: +6.3dbm, frequency tuning range: 10MHz. In the end, the phase noise performance of subharmonic sampling phase-locked loop and digital PLL using frequency divider are analyzed and compared. The result shows that the former has more superior phase noise performance if both of the PLLs use the same reference and VCO.