Design Of A Low Phase Noise Phase Locked Loop For High-speed SerDes Circuit

With the rapid development of high-speed wireless radio frequency communication technology and integrated circuits,traditional parallel data transmission methods have been unable to meet longdistance high-speed data transmission.Ser Des serial transmission interface has gradually become a popular high-speed interface technique.However,the signal transmitting module and receiving module in the Ser Des circuit requires an accurate and stable clock circuit to cooperate with the data for the correct transmission and reception since the size of the clock signal jitter directly affects the transmission and reception of data.This thesis designs and implements a low-noise,fast-locking highperformance phase-locked loop(PLL)chip,which is applied to the clock generation circuit of the12.5Gbps Ser Des transmitter chip.The output clock frequency can be guaranteed to be continuously stable under changes and process deviations,and multi-phase and multi-frequency parallel output can be realized.A charge-pump phase-locked loop is adopted,exhibiting the advantages of low clock jitter,fast locking,small phase error,wide frequency capture range,low power consumption,and easy integration.The main research contents and results are given as follows:(1)The Phase Frequency Detector is designed with the classic three-state structure,and a configurable delay chain is added to solve the "dead zone" problem.Thus,the phase detector can still output narrow pulses to turn on the charge pump even if the frequency and phase of the input signal are the same or the deviation is small.For the charge pump circuit,the jitter caused by non-ideal effects such as charge-discharge current matching,clock feedthrough,charge sharing,etc.is deeply studied and analyzed,and effective solutions to these problems are proposed.Further,the sourcelevel switch structure and rail-to-rail op-amp are adopted to achieve precise matching of charge.As a result,discharge currents are in a wide range and the matching accuracy is less than 0.5%.(2)To ensure the loop stability and locking speed of the phase-locked loop in a wide operating frequency range,it is particularly important to design the parameter values of the passive components in the loop filter.Therefore,all the resistors and capacitors in the loop filter adopt a controllable structure,so that the performance such as the overall loop bandwidth can be reasonably adjusted as needed.(3)For the design of the voltage-controlled oscillator(VCO),an inductor-capacitor oscillator with high frequency and good noise performance is used.To ensure low phase noise performance in a wide output frequency range,a programmable capacitor array(C tank)is designed to divide the tuning frequency into 128 sub-bands for low tuning gain and reduced phase noise.Moreover,LDO(low dropout linear regulator)is designed to provide power for VCO.The power supply rejection ratio of-20 d B is obtained when the load is fully loaded,which further optimizes the phase noise of VCO.Based on the standard UMC 28 nm CMOS process,the designed overall layout area is 281μm×388μm.The post-simulation results show that the tuning range of the designed phase-locked loop is9.8～15.4GHz,which can completely cover the frequency range of 12.5±20%GHz.When the output signal frequency is 12.5GHz,the total power consumption of the chip is 36 m W,and the phase noise of-112.5dBc/Hz @1MHz can be achieved.