Methodologyresearch Of SOC Chip-Level Fast Verification

Now,the design scale of SOC is so huge and the function of SOC is so complex that the speed ofChip-Level functional simulation is lower an lower ,and more and more persons concern with theacceleration of SOC Chip-Level simulation. In this thesis,after analyzing the reason of inefficiency oftraditional Chip-Level simulation, hardware high-level modeling and co-verification is advanced toacceleratetheChip-Levelsimulation.Firstly,in this thesis,after analyzing report forms of CPU time possessed by evey partments oftraditional Chip-Level simulation, the reason of inefficiency is concluded,and the scheme ofacceleration:hardwoaresimulation andH/Sco-verficationisadvanced.Secondly,after introducing several methods of co-verification,the C-simulation method is adopted todesign the Chip-Level simulation environment.According to the C-simulation method,V2C which is thetool to translate the RTL code to C/C++ codes is introduced.Because of the high speed ofsimulation,ARMulatorisselectedtomodelingCBFMofARMISS.Thirdly,the C BFM of ARMISS is designed byextended interface ofARMulator.Using the languageofC/C++,thecycle-levelmodelof EMI(extendedmemoryinterface)andAMBAbusisdesigned.TheotherhardwarepartmentsofSOC aretranslatedtoC/C++codesusingV2C,andconnectedtoAMBAmodel,thentheChip-Levelsimulationenvironment isfounded.Finally,playing multi-media music,display of LCD picture and decoding MP3 with software issimulated intheenvironment designedinthisthesis. Accordingtotheresultofsimulation,theefficiencyofsimulation is enhanced about 20 times,and the debugging of software is easier than traditionalsimulation.Moreover, amassofdataarecreatedtodoanalysis ofsystemperformance .