Design And Verification Of A CRC Computing Core Based On AMBA

It has become a core issue in SoCs that designing and perfecting an IP core with a specific function as integrated circuits enter the System on Chip(Soc)era from the original Application Specific Integrated Circuit(ASIC)era.Because it is very frequent that data transmisses between different IP cores,it is very necessary to design and implement the check code in order to avoid the errors in the data transmission process as much as possible.Based on that,A computing module is designed and implented to generate data check code in this paper.With the introduction of the Advanced Microcontroller Bus Architecture(AMBA)introduced by ARM,it has become the industry's most popular on-chip bus industry standard.And based on that,a data interface which is mounted on the AHB bus to form an IP core integrated on the SoC is designed for the designed computing module in this paper.The cyclic redundancy check(Cyclic Redundancy Check,CRC for short)algorithm has a very strong error detection capability.It is widely used in the detection of encoders and circuits.CRC is selected as the check code in this paper based on that.Traditional CRC arithmetic methods are mostly based on serial calculation of linear feedback shift register or parallel calculation based on table lookup method.Both of these two methods is defective because it isn't configured with the input data length and CRC version.These two methods is combined in this paper to implement the configurable design of CRC parallel computing module.The computing module has two working modes,namely operation mode and check mode.The CPU can treat the computing core as a slave and write data to it according to the AHB to configure the registers.At the same time,the operation core can serve as the master of the external memory,read the data in the memory and compute the check code.After the operation of the computing core is completed,the interrupt will be enabled for the CPU to query the result.With the development of SoC,the demand for digital IC verification has risen to the same level as digital IC design.Therefore,it is necessary to perform functional verification on the designed computing core.The verification platform is set up in this paper for the computing core based on the most popular verification method Universal Verification Methodology,UVM for short.The verification platform includes two uvm?agents,ahb?agent is used to simulate the behavior of the CPU to configure the internal registers of the computing core,and crc?agent is used to simulate the behavior of memory to perform data read and write interaction with the computing core.In order to ensure the integrity of the verification,coverage-driven verification strategy is used in this paper.First,some basic test cases are written and run to ensure that the basic functions of the computing core and verification platform are correct.Then,some random test cases are written and run.Finally write a few direct test cases for uncovered feature points by reviewing the coverage report after the run is complete.The design of the computing core is finally complete in this paper,which can configure the registers according to the AHB protocol and compute the correct check code.The length of the input data and the working mode of the CRC can be configured with reading the internal registers.After the design of the computing core is completed,a UVM verification platform is established.The core function was verified using a coverage-driven verification strategy.In the end,all functional coverage reached 100%,and functional verification was complete,and the core meets design requirements.