Research And Implementation Of UVM Verification Platform Based On AMBA Bus

With the rapid development of the semiconductor industry,the scale of the integrated circuit is becoming larger and larger.The iterative speed of the chip becomes much faster with the maturity of IP reuse technology,which causes the verification workload to increase.So the verification efficiency of the chip and IP modules has become a major problem to be solved in the IC design process.It is urgent and imminent to improve the verification technology and efficiency.This dissertation carries out relevant research on UVM(Universal Verification Methodology)verification methodology and technology,designs several standardized verification components based on the AMBA bus based on UVM verification methodology,constructs a UVM verification platform based on the AMBA bus,and optimizes the random test generation mechanism in the UVM verification platform.The main work of this dissertation is as follows.AMBA bus is selected as the basic system architecture of the verification platform.Several UVM standardized verification components are designed and implemented for bus protocols such as AHB,APB,and AXI,and for general communication protocols such as UART,I2 C,and SPI.These UVM standardized verification components are reusable which can produce rich incentives to meet AMBA or general communication protocol,and can provide a strong guarantee for the full verification of relevant modules on AMBA bus.A UVM verification platform is implemented based on the above UVM components,which can effectively support to simulate a design under verification with AMBA bus interface.The function verification for an I2C-AHB controller module is carried out by using this UVM verification platform,which shows that the UVM verification platform is flexible,reusable,and has a comprehensive function that can build a perfect foundation for full verification.An improved implementation method of pseudo-random number generator and a coverage-driven method of automatic test pattern generation are proposed,aiming at the random test pattern generation mechanism of UVM verification platform.Experiments show that the combination of the two optimization methods can effectively improve the performance of the random test pattern generation mechanism,which helps to improve the random verification efficiency of the UVM verification platform.