JPEG Compression By SOPC

SOPC is a system on a single chip based on large-scale FPGA. SOPC includes soft-core or hard-core CPU,memory,I/O and programmable logic resource, which has all the advantage of SOC,PLD and FPGA. Developing a SOPC system is a process of hardware and software co-design. Hardware and software co-design enable the parallel developing of both hardware and software. Implementation of this co-design can improve the development efficiency and shorten the development period. Another advantage is to achieve objective with different means by analyzing each module's features and restriction.Based on SOPC solution provided by Altera and the computing intensive application of JPEG compression, this thesis raises an applied flow for SOPC design. This flow includes analyzing system requirement,specifying hardware and software separately,connecting hardware accelerator. C language is used to describe system. Then the system model is analyzed quantificationally by certain profiling program in order to know where the emphasis for specifying hardware and software separately is. Restriction on specification,complexity and period of designing logic are also important factor on specifying hardware and software separately.Color space conversion,discrete cosine transform and quantization are the important parts of the thesis. Custom instruction is a critical feature for SOPC system based on Nios II. An Avalon stream slave peripheral LCD Controller is also been designed to form a whole JPEG compression system.