Implementation Of FIR Filter With SOPC Technology

Filtering technology is an important branch in signal analysis and processing domain. It is the important technology to control electromagnetism noise and guarantee electromagnetism compatibility, and hence improve stability and privacy of equipment.FIR(Finite Impulse Response)filter is one of the basic algorithms for digital signal processing, which is a kind of important LTI discrete-time system, widely used in acoustic processing and image processing area. Against various implementation ways, a new way using SOPC(System on Programmable Chip) is introduced to design FIR filter, software and hardware employed.Basic theory of FIR filter is introduced in the first place. The systematic structure of FIR filter is discussed and several design theories are compared, in which Chebyshev optimal theory is emphasized. The design flow of FIR filter is also presented. The design software Matlab/DSP(Digital Signal Processing) Builder and SOPC development software QuartusII are studied in the paper, and SOPC development flow process is introduced. It includes a description of characteristic of Nios soft core and Nios hardware & software design flow process, which is emphasized.ROM megafunction block of ECG database is custom-made with QuartusII as input data. Filter coefficient is designed with FDATool in Matlab. Hardware model of FIR filter ordering 16 is designed with DSP Builder and function simulation is executed.FIR filter is designed with Matlab/DSP Builder in the following sequence, design specification, coefficient calculation, structure realization, quantification test and word length as well. The realization figure and simulation waveform are so presented. The designed model is compiled into custom instruction of Nios processor via SOPC interface, and made up hardware accelerator interface model. The result is tested by procedure with C language, and the means to download VHDL of the model into FPGA of the development kit as well.The creative work of the paper is to simplify the design process in the way of introducing custom instruction, which makes best use of the advantage of Nios to add or reduce peripherals to meet the actual requirement. In this way an instruction is operated on Nios to improve speed and decrease computing complexity.