The Full Custom Design Of 8-bit RISC MCU

This thesis has a detailed discussion on the design of an 8-bit RISC MCU with a two-level pipeline which is based on full-custom design flow. Following an introduction of computer system and architecture especially the instruction system, an overview of the designed MCU is provided. This system employs the most widely used RISC structure at present and hence has high efficiency in instruction implement. By dealing the instruction with the mode one operation in one time sequence, the operation speed is boosted and a more simplified and compact design is achieved. The set of instruction machine code is more reasonable and simplifies the design of coding controller. Each component of the designed system is comparatively designed and further optimized. Particularly, this thesis focuses on the optimization of the key operation parts like program counter, time sequence generator, ALU, the advancing carry chain and so on, so as to achieve more predominant performance and enhance the system applied frequency. Chart0.35um process is adopted. The simulation result verifies the function of the designed instruction system and the pipeline is in effect. The maximum applied frequency can reach 100MHz.