Optimization And Design Of Instruction Dispatch Unit In 600MHz YHFT-DX

YHFT-DX is a high-performance DSP designed by National University of Defense Technology, which is based on the Very Long Instruction Word(VLIW) architecture. It is implemented in 0.13um CMOS technology and its DSP core works at 600MHz. The instruction packets compaction and non-align instruction dispatch technology are used to decrease the code size, which makes the structure of the instruction dispatch unit much more complicated.To arrive 600MHz design aim, we optimize instruction dispatch unit design in several level,including logical structure, circuit and the layout design. In logical design, the instruction identifiers are used to reduce the parallel decorder logic of the dispatch unit; the pipeline stages are recomposed to balance the timing; a two-stage dispatch strategy is used to improve the performance. In circuit design, we choose the most suitable circuits, calculation the logic effort and rearrangement inputs. Critical modules such as local control signal generating logic, 8 bits priority logic and dispatch logic are redesigned in circuit level, reducing the latency about 20%. Layout design optimization is done by properly placement and route reducing technology.Via optimization, the post-layout delay of the instruction dispatch unit is decreased from 2.93ns to 1.17ns, making sure that the DSP core can work at 600MHz.The consistency among the logic, the circuit and the layout of the design is kept by hierarchical verification. Timing verification is done by the post-layout simulation. The IR-drop is kept within 1.5% with the analysis of the VCC and GND girddings.The layout area estimation method is used during the layout design, and some researches are done to reduce interconnection lines. As a result, the total layout area is cut down about 19%.Additionally, this paper introduces the domino-decode method in the design of the parallel bits decorder of instruction dispatch unit. Compared to the traditional decode methods, the domino decoder has shorter delay, much easier realization and more scalability.