Image Compression System Based On FPGA-JPEG Encoder Design

Digital images have been used widely in modern society. Because of the huge size of the raw image format, the compression technology of the digital image has become the core of the application. Till now, JPEG compression standard is more widely used since it's released by ISO/ITU in 1992.This paper presents an JPEG image compession system based on FPGA. Through improving algorithms and optimizing structures, with cinditions of efficiently using of hardware resource, the utility of the parallel algorithm is exploited more efficiently. Design an multiplication based on parallel LUT(Look up Table). The problem of time parallel is resolved with pipeline optimization algorithm, the speed of DCT is accelerated. According to the orderliness of Huffman coding table,the operation of Huffman coding can be finished using less store unit based on parallel LUT.At the same time,the speed of coding is improved. The full design is synthesized in logic, then is simulated in function and timing on EDA softwares. The result of synthesis and simulation indicate that the design can give a better performance on speed and resource using with less hardware resource and a higher frequency, and can meet the requirement of real-time application of JPEG image processing.JPEG image compression system carried on hardware verification. Use ADV7181B realization AD conversion.Use TMS320C6416 realization system configuration and connecting with PC through a PCI bus. Use Microsoft VC++6.0 development environment developed system software, realization the control of whole image compression system.