Research And Design Of M-JPEG Encoder And Decoder Based On FPGA

Motion JPEG or M-JPEG (Motion Joint Photographic Experts Group) is a kind of video compression format, where each frame is encoded separately using JPEG. It not only follows the various advantages of JPEG, but also successfully applies JPEG to moving images. Currently, it is widely used in many kinds of electronic consumables such as digital cameras, camcorders, mobile phones, remote medical, desktop video systems and so on.Research work focuses on the design of FPGA-based M-JPEG codec. Design idea of codec is proposed on the general prospect after brief introduction of JPEG standard and FPGA design method. First, algorithms of M-JPEG codec are studied in depth; Then, each design model is described in detail; Last, all main models of M-JPEG basic mode codec are realized using HDL hardware description language and function simulation waveforms and test results are presented.The main contents of the research include the following aspects:1. Chen DCT fast algorithm is studied and two-dimensional DCT transform module is designed. In the design of two-dimensional DCT transform module, technologies, such as parallel operation, ranks of decomposition, ping-pong operation, resource sharing and pipelining, are used to realize the DCT transform algorithm; Combined with simulation results and compiling reports, this module not only improves the speed, but also reduces the consumption resource, gains a balance between the area and the speed, and quickly and efficiently completes the 2D-FDCT treatment; 2D-IDCT is also realized using the same method;2. Integration of the quantizer and the scanner module not only reduces the memory consumption, but also saves the running time; Entropy coding module is designed using the lookup table method, and finally the encoded data are output in the format of fixed length 32bits in accordance with the standard format, and simulation results are also given for each module;3. In the design of entropy decoding module, CHT algorithm is mainly studied combining with the regularity of Huffman code table, and entropy decoding module is designed with this algorithm to reduce the judging time of decoding and memory consumption of resources. Because anti-quantitative is inherently simply multiplication operation, entropy decoding model integrated with anti-quantitative step not only improve the speed but also reduce the storage resources. 4. The embedded hardware multipliers of FPGA are used in the whole design, so, it not only improve the speed but also make use of no logical resources. Meanwhile, pipeline function is selected in multipliers to meet the requirements of pipeline design. Pipeline optimization technology is mainly used in the whole design to improve the system's operating frequency.The main function model's design of the FPGA-based M-JPEG codec is realized, so this project makes a exploring try to realize complex image codec in FPGA and provides positive reference to designs and implements of other image codec based on FPGA. Meanwhile, exploring the advantage of digital image processing based on FPGA and in-depth learning about the technical features of such kind of hardware design are also the significantly academic meaning of this subject.