| Intra-frame prediction is one of the important parts of H.264&AVS video encode/decode standard. The prediction block is formed based on previously reconstructiond neighbouring blocks in intra prediction mode. It has a wonderful coding efficiency. An intra-frame prediction hardware architecture which supports both H.264 and AVS standards is designed in this paper. This module is a part of the dual mode video decoder chip.At first, the video en/decode standards and their principle are introduced. Then a high efficiency hardware implement design is given base on the analysis of intra prediction algorithm in H.264&AVS. This design reuses some modules according to the common of H.264&AVS in architecture and algorithm, thereby decreases the area of chip and cost, and enhances its market competition. The parallel pipeline is also adopted to enhance the decode efficiency.The top-down design method is adopted in this design. In the beginning the system architecture and C model are designed. Then we implemented the chip by Verilog HDL. After FPGA verification is passed, the ASIC synthesis, which is based on SMIC 0.18μm technology library, is done by Design Complier and the netlist of chip is achieved. The results of simulation and synthesis show that the timing and area requirements of chip design are both satisfied. |