A Design Of DDR And FPGA Verification Based On LifView

According to our country' s timetable of digital video cast, simulation TV broadcast will be stopped in 2015 when the whole country' s overcast of digital video cast through wine, secondary planet and wireless channel will be realized. There is going to have a huge digital television (DTV) market requires at least three hundred million digital video decoders in the next decade in our country, and the video coding standard competition have become the competition of video decoder chip itself. Lifview product series are highly-integrated semiconductor intellectual property (IP), and are designed for standard definition (SD) or high definition (HD) digital video format. These DTV video decoders support both AVS standard of our own country and the international mainstream standards(H264, MPEG-4). The frequency in Lifview III specification is 200Mhz, DDR400 is chosen as an off-chip memory to meet the bandwidth. DDR(Double-Date-Rated) memory's complicated time request, especial the data bus, is always a trouble maker for designers. This paper gives some suggestions on DDR controller design based on Lifview project.