Research And Implementation Of The H264 Intra Prediction And Deblocking Filter

H264 video compression standard is known as the new generation of video coding standard due to the higher performance. Compared with the H263 and MPEG-4, H264 digital rate can be half lower in the same quality of image reconstruction, or the SNR significantly increased when the digital rate is as the same of H263 or MPEG-4. The fields of the video communications and digital television broadcasting will be promoted greatly, because of excellent data compression and network compatibility of H264.The algorithms and logic hardware implementation of intra-prediction and de-block filter modules of H264 were studies in detail in this dissertation. Because there are many additions and multiplications existed in Intra prediction module's various forecast models, and some of the same operation results were included among these various forecast models meanwhile, a reducing algorithm was developed to reduce significantly the redundancy and got a high degree of parallelism in this paper. The current predicted pixel value can be obtained directly without a additional calculation if this pixel is predicted previously. De-blocking filter need to read-write operation to the external memory, but not at full time, therefore, the filtering process used alternately with the external memory read and write. Meanwhile, the filter changed sequence in order to reduce the delay of output data, in which a smaller circuit area and a high filter computing power achieved. The main work of the entire paper is described as follows: First, the performance of the H264 decoding and deblocking algorithm was simulated by Matlab using codec provided by JVT, the simulated data for the coming hardware test was generated also in the mean time. Then the verilog progam of the completed intra prediction and deblcoking filter modules was developed, the circuit functional simulation processed in Modelsim using simulated data generated in matlab. The simulation results reflected that RTL-level circuit was correct.At last, the synthesize simulation and the perfomanse verification uesed xinlinx's ISE software and the VirtexII XCV6000 board platform to complete, the test result and the Matlab simulation result were consistent. All the performance analysis algorithms are used in 24bit fixed-point data to meet the need of the accurate of data. At last, the ultimate goal of the modules can meet the need of the Intra prediction and deblock filter at 720×480 standard video format at 30 frames/s fixed-point data to meet the need of the accurate of data.