FPGA Implement Of Burst Packet Assembly Module In Core Function Board And Core Module In Transceiver Board Of LOBS Network Edge Node

In recent years, OBS (Optical Burst Switching) that combines the best of OCS and OPS is proposed to meet the increasing demand as it could provide rapid resource allocating and high network usage with relatively low optical technology.The paper is based on the 863 project, "OBS key technologies and experimental system", and provides the design and implement in the core module of the core function board and the transceiver board of the edge nodes, specially concentrates on burst packet assembly module of the core function board, which plays a significant role in the edge nodes.Chapter 1 introduces the background of LOBS technology, and its architecture and key points. And then, indicates the main content of this paper.Chapter 2 indicates the components of the edge node of the LOBS Network, which is mainly composed of core function board and transceiver board. Both core function board and transceiver board are composed of some hardware modules, for example G-bit Ethernet PHY chip, parallel to serial IC S2064, SDRAM, FPGA, etc. The paper introduces the hardware resources, especially concentrates on the interface of FPGA and other hardware resources.Chapter 3 describes the FPGA implement details of the modules of edge node of the LOBS Network. This Chapter is composed of two parts: the burst packet assembly FPGA in the core function board and the FPGA in the transceiver board. On burst packet assembly FPGA, data and information are stored respectively, and arithmetic only process the information, which makes assembly arithmetic efficiency. When assembly, the arithmetic demands and renews the FEC table real-timely. When write/read SDRAM, arithmetic uses burst page mode, and divides SDRAM memory efficiency. The paper also introduces the FPGA implement of core module of "transmitting direction" and "receiving direction" on transceiver board, the main function of the FPGA is synchronizing the input data and transmitting them.Chapter 4, is mainly about the conclusion of this paper, analysis the key points in designing of the edge node, at last, propose the improvement method to achieve higher performance. The arithmetic in this paper is developable, it can support self adaptive assembly arithmetic in small modification.