The Design And Application Of The Peripheral Circuits In Large-capacity SRAM

A large portion of the silicon area of many contemporary digital designs is dedicated to the storage of data values and program instructions. More than half of the transistors in today's high-performance microprocessors are devoted to cache memories, and this ratio is expected to further increase. Depended on its fast access speed and its low power, Static Random Access Memory (SRAM) is a great part of the memory family. SRAM have been implemented in many high-tech chips involving multi-media, compressing and decompressing of video signals, transferring TV signals, digital orbiter system and etc. The high-speed and low power SRAM has become a hot research area in today's digital research fields. The memory unit is the core of the memory, whose structure is relatively fixed, and whose performance is determined by the current process. So people pay more attention to the peripheral circuits (such as decoder and sense amplifier) of the memory when they design the SRAM.In this thesis, the peripheral circuits of SRAM were designed on discussing its whole structure. Firstly, the thesis presented a new heuristic design method for design the sizes of a CMOS logic chain with fixed long interconnect wire. The simulation proved that the decoders using the design methods can save 20% power and 15% layout area than it designed with the traditional methods. Secondly, A high-performance Sense Amplifier (SA), were designed on the analysis and summarization of three types of basic SA structures. At last, the peripheral circuits were used in a 256K×1 bits SRAM, from carefully simulation of the whole circuits, it is estimated that the typical parameter were the access time.