SRAM Test Design And Implement Based On March C-Algorithm

The design and implement of bit-oriented Static Random Access Memory(SRAM) test circuit based on March C-algorithm is presented in this paper. The test bench is based on the test board of the Neusoft Group Fire Wall Project. 256K*16 bit Radom Access Memory(RAM) is used on the board. The RAM is tested by March C-algorithm implemented circuit.In order to secure the reliability of board level SRAM, the test circuit is designed based on board-level SRAM Built-in Self Test(BIST) design. Because various fault model of board level SRAM should be considered, the March C-algorithm is used. Based on the traditional bit-oriented optimal March C-algorithm, the byte-oriented optimal March C-algorithm is presented. The algorithm can test combined faults with bytes and data maintenance faults of the SRAM. The failure coverage rate is up to 99% to delay faults, abrupt faults, open-circuit faults or address decoder faults. Besides, With increasing of a small amount of cost, a BIST controller with a memory built with FPGA is used to meet the requirement of SRAM testability.The design method of the test circuit is from top to bottom. The simulation is implemented with Verilog HDL language. First, the test vectors are obtained with analysis of the March C-algorithm. Those test vectors are stored in the fixed units of FPGA. Second, the writing order of the vectors is obtained with the March C-algorithm. An algorithm flow chart is extracted from the order. Verilog HDL language is practically needed for simulation on the order and verifying the correctness. Then, the data pass and state exchange diagram are formed with algorithm flow chart. The data pass is used for storing data such as test vectors, read and writ SRAM orders, control bytes which may be used in test. The state exchange diagram consists of state signal output and state jump conditions, it can be implemented by FSM(Finite State Machine). Finally, a digital system is linked with data pass and state machine. Therefore, the system can implement the SRAM test.The designed test circuits can be used for testing independent SRAM models. They can also be the Built-in Self Test circuit to test embedded SRAM.