Design Of Embedded Memory Build In Self-Test Algorithm On ARM Cortex M3

Recently, as the function of the chip is becoming more and more diversifying, the demands for embedded memory are rising up rapidly. The density of memory can be very high with advanced manufacturing process, but more complex defects emerge under the process, such as 3-cell coupling faults, and the defects can increase chip escape rate, so the chip quality cannot be guaranteed. Memory build in self-test(Mbist) has been one of the main methods of memory test, which has advantages of low test cost and few dedicated pins, it is important to study the algorithm for 3-cell coupling faults testing.In this paper, deep researches on 3-cell coupling faults and memory build in self-test algorithm for these 3-cell coupling faults have been carried out. The algorithm is designed on the complexity and fault coverage. Firstly, the behaviors as write-destroy or read-destroy or incorrect transition of the 3-cell coupling fault is analyzed in this paper. According to different fault behavior, the 3-cell coupling faults are divided into seven categories and are established by using the fault primitive. Then, during the analyzing testing process of March and S3CTEST algorithm, it is found that the existing algorithms have the disadvantages of long testing time and low coverage rate on 3-cell coupling faults, so a new test algorithm 3C March is proposed. The new algorithm adopts the optimized background data initialization steps and the sensitization steps, all logical value combination of three elements can be achieved by these background data initialization steps with a low algorithm complexity, and the sensitization steps can detect existing 3-cell coupling faults, what’s more the fault coverage for 3-cell coupling faults is 100% and complexity of the algorithm is 78n.A 512x16 SRAM of ARM Cortex M3 has been used for verifying March 3C on feasibility and validity, the clock period is 5ns and the test time of March 3C is about 196us. The result is that this algorithm has short test time and full fault coverage. Achievement of this paper can be used for testing SRAM in chip, which can improve yield and reduce the cost of chip.