Design, Based On March C + Algorithm Mbist

With the rapid development of VLSI technology, the capacity of embedded memory in chip is getting larger and larger, especially in an SOC (System on Chip). On the other hand, as the feature size of devices shrinking down further, the possible fault models become complex. All of these factors result in the increase of test time and test cost. So how to screening out logical failure of the product is an important aspect of the VLSI test.Considering the fault types, test equipments, test throughput, high-speed and test cost, Built In Self Test (BIST) technology is known as the most efficient strategy for the embedded memory.First of all, the fault mechanisms and fault models of embedded memories are investigated. The importance of the DFT technique for the memories is discussed and several implementation methods are introduced. Then, deeper discussions about several test algorithms are given. By comparing them with each other, the conclusion that March C+ may be the most efficient algorithms for memory test is obtained. Finally, a RAMBIST circuit which based on March C+ algorithm is designed and the algorithm is simulated. The comparison and analysis are carried out between the experimental data and the existence data. Comparing with the traditional BIST structure for RAM, the new one is reusable, compact, rapid and of high fault coverage. Therefore it can be considered as a practical and prospective scheme.