The Analyse And Design About Meta-Stability In Asynchronous Timing Circuits

In many designs of IC, ASIC, FPGA, more software can help engineers to build several million gates circuit, but all the programs can't solve the problem of signals'synchronization. The designers need know more reliable design skills in order to decrease the risk of multiple clock domains. It's very important to synchronize the signals when design digital circuits, especially input a signal through a different clock domain. The asynchronous input signal must be synchronized, otherwise the circuit will not be able to work normally, and it will lead to meta-stability and wrong sampling. This paper makes some analyses on meta-stability for its cause and harm. The paper also provides a new method to solve the problem of meta-stability and manage to verify the method with UART model.