The Design And Implementation Of Security SOC Chip UART Interface

With imports of IC products beyond petroleum to become China’s first imported goods, the national investment and support efforts to further increase the IC industry, IC industry has entered the best stage of development. Because of its obvious advantages in product development cost and development cycle, SOC (System on Chip) has greatly improved the competitiveness of their product. SOC will rapidly become a mainstream technology and direction of the VLSI, there are good prospects for its development.As the internet finance continues to penetrate into the various walks of life, the security of personal information and property is also becoming more and more important. Information security is not only important in the military field, is also crucial in civilian areas. A high quality security SOC chip, in order to meet different application, not only need to be integrated with a variety of common security algorithm, but also need a number of high-speed and secure external I/O interfaces for safe storage of information.UART (Universal Asynchronous Receiver/Transmitter) is a widely used serial data transfer interface. At present, most of the chips are integrated UART interface, which has a very wide range of applications. This paper describes the design of a UART interface in the secure SOC chip, including asynchronous FIFO module, transmits data module, receives data modules, and so on. Before the design, we carried out extensive research on the universal design methods of market. After a serious and rigorous consideration, we worked out the design plan of the UART interface for this security chip. Throughout the design cycle, we conducted verification of modules, modified the design in a timely manner, detected the design deficiencies, and constantly optimized the design. At the same time we carried out the RTL level simulation, FPGA verification and final test after the tape out of the chip to ensure the reliability and validity of the entire design.After the tape out of the chip, the results of final test show that the design is functionally correct to meet the design requirements and meet the needs of customers.The work of this design has achieved the following innovative results:Increases the transmission speed and expands the transmission quantity. Taking into account the diverse needs of customers in the practical application, the design adds one level FIFO, four level FIFO, eight level FIFO, sixteen level FIFO mode. In order to break through the bottleneck of speed, we designed to optimize the testing procedures of receiving data, and data sampling points. This allows the design several times faster, greatly improving the efficiency of the interface.The communication clock and system clock of the interface crosses different clock domains, to achieve a cross clock domain design. The design supports the situation of the system clock faster than the communication clock, and the communication clock faster than the system clock. The design supports any multiples of clock relations to meet the various needs of users which greatly improves the degree of freedom and efficiency.The interface design based on bus interface makes it support byte (8 bits), half word (16 bits), word (32 bits) access, which improves the portability of the module. This also supports low-power modes, improved product advantages.