Design And FPGA Implementation Of Turbo Decoder

Turbo coding is a new coding method, which objective is to achieve the Shannon limit according to a new coding algorithm. The objective of the paper is to study how to design a Turbo decoder used in the third generation code-division multiple access system, which will be realized by FPGA.Firstly, researching the Log-MAP decoding algorithm of Turbo code, primarily optimizing the computing method of forward route and back route through introducing the sliding window technique, so as to reduce the decoding delay and save the storage space.Secondly, based on the research on the sliding window Log-MAP decoding algorithm of Turbo code, analyzing the integrated structure of decoder and designing a pile line structure that can be realized with hardware.At last, realizing a pile line structure of Turbo decoder with hardware circuit, including decompose multiple connection receiving data circuit, calculating the branch metric, calculating the forward path and the backward path, by the application of the FPGA technique as well as the 3G criterion specified data rate. Then, we also analyze the simulation result further.Furthermore, analyzing the structure of interweave component realized with hardware circuit.