Functional Verification Of SoC Based On 51 IP Core

With the booming of the scale and complexity of IC design, accompanied by the enormous pressure of time-to-market, the reliability of verification is getting lower and lower. Indeed, SoC design verification accounts for 70 percent to 80 percent of the total product development time. Chip verification, especially functional verification has become one of the most difficult and challenging issues in IC design.Based on the background of the scientific and technological project in Shandong Province-"The ASIC Design of Gas Volume Controller", this paper discussed the functional verification of this SoC.Firstly, this paper discussed the current major functional verification methods; focused on improving the efficiency of functional verification, and applied them in practice. Secondly, to ensure the functional correctness of modules, we introduced the functional verification of modules at the stage of hardware code design. And in the verification process, we strived to improve the degree of automation and the reusability of verification platform to shorten the time. Thirdly, we discussed the significance and implementation strategies of co-verification. We adopted the combination of HDL simulator and FPGA prototype to validate system level design. Built the co-simulation environment using HDL simulator, discovered and solved the SoC hardware and software interface and timing issues, improved system performance of the chip. Fourthly, we built rapid modeling of the design using FPGA. Then the chip could be simulated at the speed close to the actual environment. And on this platform we could also develop application program; detect issues which existed in the actual system, as well as the possible problem may exist between driven software and chips in the early age. It would greatly reduce application development time. Finally, we made a simple conclusion of the experiences we got in this item.