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Research And Implementation Of Integrated Data Optical Synchronous Network Node Ethernet Gateway Interface

Posted on:2009-01-01Degree:MasterType:Thesis
Country:ChinaCandidate:J C ZhangFull Text:PDF
GTID:2178360245499447Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Wideband Integrated Data Optical Synchronous Network was designed by our project team according to the needs of modern network development with independent intellectual property rights of the new network. The optical fiber is the transmission medium, enables the system to have the huge band width capacity, like this transmits the band width bottleneck to be able to solve; adopts high speed multi-processor which composed of system on programmable chip to enable the system to have the enough information-handling capacity; moreover because uses the brand-new dynamic data current capacity adjustment the concept, it will be enable us to have the infinite imagination space to its future. Using relevance technologies such as FPGA, SOPC, it will be able to transfer integrated business information such as document, voice, image and data conveniently, with high real-time performance, high reliability, high flexibility and efficiency of the characteristics, the application prospect is broadly.Wideband Integrated Data Optical Synchronous Network is mainly composed of the network concentrator part and the user node part. This topic mainly completes the basic function of node Ethernet gateway interface. Combine the current development situation, proposed the embedded Ethernet gateway interface solution. Take the NIOS II embedded processor as the core, using Ethernet controller DM9000A, has designed the Ethernet gateway interface based on the NIOS II embedded processor. So far has completed the Ethernet gateway interface concrete hardware design plan as well as under the QUARTUS II platform related modulation design, has compiled the node computer correspondence part related protocol as well as the gateway interface driver. The test result indicated that this design has completed the essential requirements function. Compares with the traditional embedded design proposal, this plan using FPGA, SOPC and so on correlation technique has the very strong extension and the flexibility, reduced the development cost and the hardware realizes the risk.In addition the topic has designed the data administration implement for node part, with the aim of realizing the data memory repeater, and proposed several methods for error control, by comparing the good and bad points of these algorithmic to show the error control algorithm's development and the improvement, so the application staff can use a more rational algorithm to optimize the network transmission performance.
Keywords/Search Tags:WIDOSNet, Gateway interface, NIOS II, FPGA
PDF Full Text Request
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