A SONY 0.47 M Pixels Digital Vedio Presenter System Based On IZAS Image Zoom Algorithm

The paper brought forward a new design of digital video presenter on baseof FPGA. The video presenter converts manuscript, picture, object andinformationin in other forms into image signal and outputs to projecter, monitorand other display equipment. Therefore it owns such a large utilization in fieldsof education, conference, product presention and so on. Whileconventioanl Analog video prenster is not satisfied for its unclear and non-stableand glint picture, furthermore its image is remarkbaly subject to the enviroment.In this thesis, the reserch focused on image processing technique and the FPGArealization along with an application system based on FPGA and thus solvingthe problems.Firstly, the technique of image real-time magnification by FPGA is adopted in this research. The zoom arithmetic which could fulfill the demands of the video presenter is chosen to be the research objects. By using the assured zoom scale search a simple,higher precision core function of easily implementing. Re-sampling to its continuity model can obtain the zoomed pixel value and then the original image will be effectively magnified from 738x575 to 1024x768, just using 3 double port RAM embedded in the FPGA as the image signal buffers.Secondly, The PAL format YUV(4:2:2) signal from image sensor, a kind of measure of colour space transformation is used in, then is converted into RGB(5:6:5) format.Thirdly, the paper also carried out a kind of more compact scheme for video presenter which could transform interleved scan into linered scan, just by using one SDRAM as frame buffers, the image signal is de-interlaced with the field interpolation algorithm and the frame rate is speed up to 60Hz from 25Hz.At the same time, in FPGA, realizes the driving to optic lens'step motor and PS/2 mouse, so the mouse cursor can be displayed on the screen. It also realizes the function of image freezing, negative image display, color/black switching and image/text switching. The whole design is written in VHDL, and it is fulfilled in the Xilinx Spartan3E series FPGA XC3S250E with the developing environment of ISE8.1.