The Research Of Digital Video Presenter Based On FPGA

Video presenter can convert the manuscript, picture, object and other things to image signal and display it on the projection, monitor and other display equipments. So video presenter is widely used in education, meeting, product presentation and other fields. Digital video presenter has the advantages of image clear, non-glint, color trueness and function extend easily compared with analog video presenter. Therefore, it has much usage merit and will be widely used.The paper takes Sharp 470 thousand pixel color CCD (Charge Coupled Device) image sensor set to capture the image signal and use FPGA to dispose the signal, so the signal can be displayed on the VGA monitor real-timely. The design scheme is less costly than adopting special image processing chip and it can extend system functions easily. The main works of the paper can be summarized as follows:(1)Design of system hardware structureThe paper realizes the hardware circuit design of image signal capturing, image signal processing, signal output and control module.(2) Realization of image format convertion and frame rate up-speedingThe paper utilizes FPGA to convert the PAL digital YUV(4:2:2) format image signal outputted by CCD image sensor set to RGB (5:6:5) format. Using two SDRAMs as frame buffer, the image signal is de-interlaced with the field interpolation algorithm and the frame rate is speeded up to 60HZ from 25HZ.(3) Realization of image magnificationBy utilizing Block RAM in the FPGA as horizontal buffer, the image resolution is magnified from 738*575 to 800*600 with the linear interpolation algorithm, which is SVGA (Supper Video Graphics Array) format.(4) Realization of the driving and display of PS/2 mouse According to the PS/2 protocol, the paper realizes the initialization toPS/2 mouse and the moving of the mouse can be displayed on the screen. The horizontal and vertical synchronization signals of SVGA@60HZ are generated simultaneously.(5) Proposal and realization of an improved autofocus algorithmThe paper proposes an improved gray scale differential algorithm as focus value. The sum of the gray scale differential absolute values of an image is used as the focus value. FPGA compares the focus value of two adjacent fields (odd field or even field) and transmits the comparing result to the single chip microcomputer. According to the signal, the single chip microcomputer controls the moving of the step motor with some search strategy, so the function of autofocus can be implemented.(6) Implementation of some assistant functionsThe paper implements some common functions used in the video presenter, such as image freezing, negative image display, color/black switching and image/text switching.The whole design is written in VHDL, and it is fulfilled in the Xilinx Spartan3E series FPGAXC3S250E. The design is already used in the video presenter production. The implemented function modules in the paper can be used in this system, but also in other systems as the independent and owned Intelligence Property IP core.