Research Of Algorithm For Video Coding And The Realization Of FPGA Based On H.264

Recently, with the development of broadband and multimedia processing techniques, video compression technology has become a hot spot. International telecommunication Union (ITU) and International Standardization Organization (ISO) have put forward a series of international standards for video coding. In 2003, a new video coding standard named H.264 was released formally. Promised on the same video quality, video coding based on H.264 is more effective than any other coding standards. On the same time, the newly standard has network friendly design and strongly error control in transmission.Motion estimation is a key technology of video coding standard. Motion estimation and motion compensation can reduce the large amount of temporal redundancy that exists between frames of video sequences, which leads to high compression. So how to make the search of motion estimation algorithms that faster and more effective becomes a hot research topic.Firstly, in this paper the principle of video coding is introduced briefly. Especially gives an overview of H.264 standard, include the processes of coding and decoding, main framework and specific technologies and so on. This paper is based on these content.Secondly, the principle and technical indexes of block matching motion estimation are discussed in this paper. By studying the existing rapid motion estimation algorithms, MTS is proposed that has better performance and can be easily realized in hardware. This algorithm employs a small diamond pattern to search the center area based on the first step of rough search, which could improve the effect of small motion estimation near the center area. According to matching criteria, a best match block will be found. The proposed algorithm is used based on JM software model, PSNR,Coding time and Bit rate were tested, The test results indicate that compared with FS and TSS , MTS improves coding speed ,saves the time of motion estimation and has better search performance.At last, this paper study how to complete the hardware architecture design for MTS. MTS has regular data stream and has some common characteristics with FS. Therefore, An architecture implemented on FPGA is designed for MTS, This architecture is developed from the structure of YANG for FS. Moreover, function modules of MTS motion estimation algorithm are set off, mainly include: on-chip memories, on-chip memories control, the function module of process array, SAD selector, and so on. Each function module was designed and implemented with VerilogHDL, and function simulation was accomplished in QuartusII, finally, the rtl-level circuit diagram of every function module was obtained.