| With the rapid development in the area of computer technology and communication technology, digital video plays a more and more important role in information society. While the development of high-speed digital signal processor and Very Large Scale Integrate circuit (VLSI) makes real-time video compression and transportation possible.This dissertation presents the study of several issues in video coding and its hardware implementation. A novel hardware-based video coding system is proposed based on the ITU-T H.263 Recommendation. Some key techniques such as Discrete Cosine Transform (DCT) and its inverse (JDCT) and motion estimation are studied in detail.The main contribution of this dissertation includes three aspects. Firstly, the relation between the computation precision and complexity of DCT/IDCT and their resource requirements is studied, a scheme for DCT/IDCT implementation based on row-column decomposition and Distributed Arithmetic (DA) is proposed. And their performance is enhanced by optimizing the data flow path. Secondly, the performance and computation complexity of various kinds of motion estimation algorithms are analyzed and evaluated. A kind of hierachical quasi full search scheme is proposed. Its computation complexity is greatly reduced compared with full search while its match effect is still satisfying. Finally, these two schemes are implemented with FPGA.
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