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Assertion-Based Verification Research And Application

Posted on:2009-05-31Degree:MasterType:Thesis
Country:ChinaCandidate:L H LiangFull Text:PDF
GTID:2178360248954786Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Functional verification is one of the challenges in modern IC design, it has become a bottleneck in the IC design process. The main content of this paper is ABV(Assertion-Based Verification). ABV combines assertion technique in formal verification with simulation, makes use of monitor features of assertions, finds design bugs quickly in the simulation process. Also the observability and the controllability have been improved by use of ABV. ABV method is one of the most popular techniques that discussed in functional verification field.By comparing the performance and cost of several typical assertion verification formats, the OVL (Open Verification Library) is adopted to build assertion IP module, the paper will introduce the realization and the application of OVL. AVL is created on the basis of OVL to check some special property, AVL is an important supplement to OVL.This paper has done the verification job by ABV in General Purpose Bus Controller Module in Mobile Project, and has introduced the method how to apply ABV to verification work. General Purpose Bus Controller is a module of SoC Product that based on embedded processor. The verification method used in this paper combines assertion with simulation. Test incentive mechanism is Constraint Random method. First of all, popular verification environment is built in this paper which is based on transaction method, then the modules of Sequence, Generator, Bus function models and Checkers are designed and introduced. Different properties of APB interface, NOR FLASH interface, NAND FLASH interface protocol are picked up, and assertion IP based on OVL and AVL are created and inserted into the verification environment, then the actions of interface are monitored. These assertion IP modules build in this paper towards special interface above can also be used to monitor other projects with the same interface. The results showed that, the functional verification method discussed in this paper is effective to find design Bugs, and can ensure the success of IC design.
Keywords/Search Tags:Functional verification, Assertion-Based Verification, Software simulation, Open Verification Library
PDF Full Text Request
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