Study On Assertion-based Functional Verification Of PCI Bus Controller Core

With the rapid development of integrated circuit technology, the size and complexity of chiphas been quite different. The traditional verification method is no longer applicable for thedesigns with current complexity. Verification has become a bottleneck of the entire chipdevelopment process. Many advanced techniques, such as transaction-level verification,constrained random stimulus generation, coverage-driven verification, verification IP,assertion-based verification and advanced verification methodology, have become themainstream for hardware verification. Among them, the assertion-based functional verificationtechnology has many features, such as reducing the code of verification platform and quicklylocating design flaws, etc., which has been an important verification technology.This dissertation researches on the functional verification of PCI bus controller.Configuration graph is used to describe the configuration generation process of the controller. AConfiguration graph based transaction generation algorithm is proposed. And an assertion basedverification IP is designed and implemented. Firstly, we describe the problems and challenges ofhardware verification and the features of several popular advanced verification techniques. Thenwe use the PCI bus controller as the design under verification to describe an entire verificationflow in detail, including the design of verification plan, test requirements and test cases, and thedevelopment of verification platform. To enhance the integrity of verification and the efficiencyof stimulus generation, a transaction generation algorithm based configuration graph is proposed,which achieves efficient generation of PCI target device interface transactions. Finally, toimplement the functional verification of PCI bus controller core, an assertion based checker isdesigned as a verification IP core within VMM architecture. And the running results of thechecker are analyzed and summarized.The verification results show that, PCI bus protocol checker can quickly locate designerrors, enhance the controllability and observability to the verification process and can be reusedin another verification environment easily which need verify the PCI interface. The checkershortens the verification time, and improves verification productivity and quality.